The audio amplifier ASIC was a stereo digital audio amplifier running up to 7W per channel. The digital, analog, and power sections were placed on a single die providing the end customers with a single chip solution. The optimization target for the ASIC was low cost and low area. Thus, extensive area reduction techniques were utilized to optimize the size and cost of the chip.

The front end digital portion of the ASIC took SPDIF or I2S at the input, performed volume control, up sampling, digital power supply rejection, parametric equalization, and H-Bridge control. The various parameters were configurable via an I2C interface. The back-end analog and power sections drove the speakers directly with minimal external filtering.

By using a strict design process, prototyping the ASIC in an FPGA, and simulating the entire mixed-signal chip in Synopsys Nanosim, we were able to achieve functional success with less than 0.3% THD on the first spin of the chip. The end customer took the first spin of the chip to market.