The bit-error-rate tester was designed to test the high speed signaling characteristics of AMD CPU sockets. Two of the Virtex-4 FPGAs were used in transmit mode, and two were used in receive mode. The patterns were configurable via software utilizing an embedded processor with a bus interface to each of the FPGAs. The transmit FPGAs would generate the software controlled pattern up to 1GBPS on each of the 160 channels simultaneously, and the receive FPGAs would sync on the pattern for each channel individually and measure bit errors. The receive FPGAs utilized the iDelay elements inside the Virtex-4 FPGAs to control the capture edge. This was used to not only center the capture clock, but to also adjust the capture clock back and forth to measure the size and characterize the valid data window.