Developed and tested the HDL for the mixed-signal ASIC. The ASIC HDL was ported to a Xilinx Spartan3-1200E device. The Xilinx development platform was used to verify the multiple channel audio receive functionality beyond that of standard simulations. The simulation effort took the form of a file reader system verification environment. The stimulus files to drive the receive functions were generated via a C# application that was also used to configure and monitor the Xilinx development platform during FPGA hardware functional test. The receive functions, coded in Verilog, were responsible for correlating the serial bit-streams to the extracted clock, parsing the serial audio data from the appropriate channels, and presenting the 16-bit volume controlled audio to either an I2S interface or a D-Class audio amplifier. The capability to mix I2S input and system tones were also implemented. The system tones were either generated via a programmable CORDIC algorithm or a simple lookup table.